The present invention relates generally to integrated circuit design tools, and, more particularly to an integrated circuit design timing path verification tool.
An application-specific integrated circuit (ASIC) design flow includes several stages and begins with a design entry stage in which an integrated circuit (IC) design is defined using a hardware description language (HDL). The design entry stage is followed by a logic synthesis stage in which HDL (Verilog) and logic synthesis tools, such as an RTL Compiler (RC) are used to generate a netlist that includes a description of each digital logic element and its connections in the IC design. This is followed by a pre-layout simulation stage that validates the operation of the IC design by running unit-delay, gate-level netlist simulation on the IC design. During this netlist simulation, each digital logic element is assigned a propagation delay of exactly one simulation time-unit. The pre-layout simulation is followed by floor planning, placement and routing stages in which the generated netlist is arranged on a die and additional routing connections are made. Finally, post-layout simulation is performed with delays for each logic element being back-annotated from the floor planning stage.
Upon completion of the design stage, the IC design is verified for timing performance by checking all possible timing violations in all possible timing paths that connect any two flip-flops in the IC design. The timing paths include digital logic elements, such as AND, NAND, and NOR gates, and other combinational logic circuits. One type of timing analysis includes static timing analysis (STA). During STA, each timing path is verified for timing violations using an external clock as a reference, and timing constraints for each timing path are stored in an STA report.
Timing paths are generally of two types: single-cycle and multi-cycle timing paths. If a data signal crosses a timing path within one clock cycle of the external clock signal, the path is defined as a single-cycle timing path, and if the data signal requires more than one clock cycle of the external clock signal to cross the path, the path is defined as a multi-cycle timing path.
Sometimes single-cycle timing paths are erroneously defined as multi-cycle timing paths, and vice-versa. There are several reasons for such incorrect definitions, such as a knowledge gap due to lack of accurate design constraints or involvement of third party vendors in design verification stages. Also, sometimes the number of clock cycles required to propagate a multi-cycle timing path is incorrectly defined. For example, a multi-cycle timing path that requires four clock-cycles to propagate may be wrongly defined to require five clock-cycles to propagate.
Such incorrect multi-cycle exceptions are caught late in the design cycle while performing back-annotated post-layout timing simulation during the post-layout simulation stage. In back annotation, propagation delays corresponding to the digital logic elements of a timing path are fetched from a source file (e.g., a Synopsis delay format (SDF) file), applied to the netlist, and then the IC design is simulated. Wrongly defined timing paths are identified and the STA constraints for those paths are modified. Since the STA constraints have been modified, the IC design has to undergo the entire ASIC design flow once again, which is time-consuming and significantly delays chip tape-out.
Therefore, it would be advantageous to have a system and method that successfully validates an IC design and detects wrongly defined multi-cycle timing paths, and detects wrong multi-cycle exceptions at an earlier stage in the ASIC design flow.